The technology of making interconnections for providing vias, lines and other recesses in semiconductor chip structures, flat panel displays, and package applications has been developed for many years. For instance, in developing interconnection technology for very-large-scale-integrated (VLSI) structures, aluminum has been utilized as the primary metal source for contacts and interconnects in semiconductor regions or devices located on a single substrate. Aluminum has been the material of choice because of its low cost, good ohmic contact and high conductivity. However, pure aluminum thin-film conductors have undesirable properties such as a low melting point which limits its use to low temperature processing, possible diffusion into the silicon during annealing which leads to contact and junction failure, and electromigration. Consequently, a number of aluminum alloys have been developed which provided advantages over pure aluminum. For instance, U.S. Pat. No. 4,566,177 discloses a conductive layer of an alloy of aluminum containing up to 3% by weight of silicon, copper, nickel, chromium and manganese was developed to improve electromigration resistance. U.S. Pat. No. 3,631,304 discloses aluminum alloys with aluminum oxide which were also used to improve electromigration resistance.
More recently developed VLSI and ULSI technology has placed more stringent demands on the wiring requirements due to the extremely high circuit densities and faster operating speeds required of such devices. This leads to higher current densities in increasingly smaller conductor lines. As a result, higher conductance wiring is desired which requires either larger cross-section wires for aluminum alloy conductors or a different wiring material that has a higher conductance. The obvious choice in the industry is to develop the latter using pure copper based on its desirable high conductivity.
In the formation of VLSI and ULSI interconnection structures such as vias and lines, copper is deposited into a line, via or other recesses to interconnect semiconductor regions or devices located on the same substrate. Copper is known to have problems at semiconductor device junctions due to its low electromigration resistance. The electromigration phenomenon occurs when the superposition of an electric field onto random thermal diffusion in a metallic solid causes a net drift of ions in the direction of the electron flow. Any diffusion of copper ions into the silicon substrate can cause device failure. In addition, pure copper does not adhere well to oxygen containing dielectrics such as silicon dioxide and polyimide.
U.S. Pat. No. 5,130,274, assigned to the common assignee of the present invention, discloses the use of a copper alloy containing an alloying element of less than 2 atomic percent by first depositing an alloy into the recess of a interconnection structure and then forming a copper alloy plug and a thin layer of an oxide of the alloying element on the exposed surface of the plug. However, the technique still does not satisfy the more stringent requirements in ULSI structures where critical dimensions of less than 0.5 .mu.m place a considerable burden on thin film chip interconnections. The use of standard Al (Cu) alloy and a silicon dioxide dielectric in a deep-submicron logic circuit wiring structure results in a large circuit delay caused mainly by the wiring connections.
The use of Cu as an alternative material to Al (Cu) in ULSI wiring structures to increase the chip speed has been attempted by others. However, numerous problems are incurred in Cu interconnections such as the tendency of Cu to corrode and the fast diffusion rates of copper in thin films. It is known that pure Cu has a smaller electromigration activation energy, i.e., 0.5-0.75 eV, than that in Al (Cu) of 0.8-0.9 eV. This implies that the advantage of using Cu for reducing interconnection electromigration failure at chip operating conditions is largely compromised.
Other workers have attempted to use copper alloys in providing enhanced electromigration resistance. For instance, U.S. Pat. No. 5,023,698 teaches copper alloys containing at least one alloying element selected from the group of Al, Be, Cr, Fe, Mg, Ni, Si, Sn and Zn. U.S. Pat. No. 5,077,005 teaches copper alloys containing at least one member selected from In, Cd, Sb, Bi, Ti, Ag, Sn, Pb, Zr and Hf where the weight percent of the alloying element used is between 0.0003 to 0.01. The copper alloys are used in TAB processes and as print circuit board members. U.S. Pat. No. 5,004,520 also teaches copper foil for film carrier application containing at least one alloying element selected from P, Al, Cd, Fe, Mg, Ni, Sn, Ag, Hf, Zn, B, As, Co, In, Mn, Si, Te, Cr and Zn with the alloying element concentrations from 0.03 to 0.5 weight percent. The alloys are used as connecting leads in integrated circuit chip mounting. Furthermore, U.S. Pat. No. 4,749,548 teaches copper alloys containing at least one alloying element selected from Cr, Zr, Li, P, Mg, Si, Al, Zn, Mn, Ni, Sn, Ti, Be, Fe, Co, Y, Ce, La, Nb, W, V, Ta, B, Hf, Mo and C. The alloying elements are used to increase the strength of the copper alloy. U.S. Pat. No. 1,960,740 further teaches a copper-indium alloy which contains indium between 10% to 50% in order to increase the copper hardness and the corrosion resistance. U.S. Pat. Nos. 5,243,222 and 5,130,274 teach copper alloys for improved adhesion and formation of diffusion barriers. However, none of these prior work teaches copper alloys that are suitable in VLSI and ULSI on-chip or off-chip wiring interconnections that has high electromigration resistance, low resistivity and high corrosion resistance. Furthermore, none of these prior work recognized the structural requirement on a microstructure level for improving electromigration resistance and consequently, none of the prior work has taught the microstructure necessary in a copper alloy in order to achieve the desirable properties.
It is therefore an object of the present invention to provide copper alloys containing at least one alloying element that can be suitably used in chip and package interconnections.
It is another object of the present invention to provide copper alloys containing at least one alloying element for chip and package interconnections that is particularly suitable for VLSI and ULSI applications.
It is a further object of the present invention to provide copper alloys that contain at least one alloying element for chip and package interconnections that have improved electromigration resistance, low resistivity and high corrosion resistance.
It is another further object of the present invention to provide copper alloys containing at least one alloying element for use in chip and package interconnections that contain about 0.01-10 weight percent of the alloying element.
It is still another object of the present invention to provide copper alloys that contain at least one alloying element for chip and package interconnections that can be easily processed by various metal deposition techniques used in the semiconductor industry.
It is yet another object of the present invention to provide copper alloys that contain at least one alloying element for use in both on-chip and off-chip interconnection applications.
It is still another further object of the present invention to provide copper alloys that contain at least one alloying element for chip and package interconnections that forms microstructures having the at least one alloying element saturated at the grain boundaries.
It is yet another further object of the present invention to provide copper alloys containing at least one alloying element selected from indium, tin and carbon for use in chip and package interconnections that form microstructures wherein the concentration of the at least one alloying element at or near the grain boundaries is at least 120% that at areas not substantially near the grain boundaries.
It is still another further object of the present invention to provide conductors formed of copper alloys containing at least one alloying element for use in chip and package interconnections wherein the conductor can withstand a current density of at least 10.sup.5 Amp/cm.sup.2.